This invention relates to semiconductor memories and more particularly to semiconductor memories having twisted bit lines.
As is known in the art, semiconductor memories include a matrix of rows and columns of storage cells (M), such cells being coupled to rows of word lines (WL) and columns of bit lines (BL). One arrangement is shown in FIG. 1. Here, the first two word lines (i.e., WL0 and WL1) connect the memory cells M to the compliment terminals C of the sense amplifiers SA and the next two word lines WL2, WL3 couple the memory cells M to the true terminals T of the sense amplifiers, and so on as the process repeats as shown. Such an arrangement requires some data de-scrambling during testing of the array. More particularly, while during normal operation, storage of a bit of data in any cell will be retrieved properly without concern as to whether the cell is coupled to the true (T) or compliment (C) terminals of the sense amplifier (SA), such is of concern during testing of the cells. For example, with a DRAM array, one test is performed where all the cells are stored with a charge corresponding to one logic state (i.e., a logic 1). To test whether the cell is storing such charge the logic state of the cells is detected with the sense amplifier. Thus, it is necessary to de-scramble the data produced by the sense amplifiers. Here, for example, when the memory cells addressed by word line WL0 are read by the sense amplifiers SA, the logic states provided at the output of the sense amplifiers in the logic are complimentary to the logic states read from the memory cells addressed by the word line WL2. The requisite de-scrambling is relatively simple in this arrangement because the complement/true condition is known by merely knowing the word line addressing the memory cells.
As is also known in the art, twisted bit-lines are used because they are less sensitive to noise and bit-line coupling. One such arrangement is shown in FIG. 2. Twist means that at a certain point in the memory array the sense amplifiers true T and compliment C terminals are swapped. Thus, as shown in FIG. 2, there are shown four regions I, II, III, and IV of a portion of the memory array. Each region has the same arrangement as the entire array shown and described above in connection with FIG. 1. However, in coupling Region I to Region II, there are bit line reversals coupled to sense amplifiers SA1 and SA3. On the other hand, in coupling Region II to Region III, there are bit line reversals coupled to sense amplifiers SA0 and SA2. The sequence repeats in coupling between Regions III and IV and from Region IV to V (not shown). The following should also be noted: Common for Regions I and III is that a word line connects the memory cells either to a true or a compliment bit line. This is different in the regions II and IV where a word line connects memory cells alternating to true and compliment bit lines. Thus, while with word line W0, for example, the memory cells are coupled to the compliment input, for word line W4 the pattern alternates between true and compliment inputs.
To put it another way, FIG. 2 shows three twist regions running parallel to the word lines. The first bit lines connected to the first sense amplifier are twisted twice, the bit lines connected to the second sense amplifier are twisted once, and so on. This breaks the array into four different Regions I-IV in the terms of physical data scrambling. Region I (i.e., word lines WL0-WL3 shows the same physical scrambling as that in FIG. 1. In Region III (i.e., word lines WL8-WL11), the physical scrambling is inverted, which means that all true and lines are swapped. Common for regions I and III is that a word line connects the memory cells either to a true or compliment bit line. This is different in the Regions II and IV. Here, a word line connects memory cells alternating to true and bit lines. It is noted that the relation between the column address and the row address for a physical data pattern is complex.
In any event, de-scrambling of the data for the arrangement shown in FIG. 2 is more complex that that required for the arrangement shown in FIG. 1.
Referring now to FIG. 3 another arrangement for a twisted bit line array is shown. Such an arrangement is used whether layout consideration prohibit the layout shown in FIG. 2; (i.e., where there is space available for only one xe2x80x9ctwistxe2x80x9d in any one row of the array). This arrangement is sometimes referred to as a diagonal interleaved twisted bit-line structure. Here the data de-scrambling is even more complex.
In accordance with the present invention, a memory is provided having an array of rows and columns of memory cells. The memory includes plurality of sense amplifiers, each one having a true terminal and a compliment terminal. The memory also includes a plurality of pairs of twisted bit lines, each one of the pairs of lines being coupled to true and compliment terminals of a corresponding one of the plurality of sense amplifiers. A plurality of word lines is provided, each one being connected to a corresponding one of the rows of memory cells. An address logic section is fed by column address signals, fed to the bit lines, and row address signals, fed to the word lines, for producing invert/non-invert signals in accordance with the fed row and column address signals. The memory includes a plurality of inverters each one being coupled to a corresponding one of the sense amplifiers for inverting data fed to or read from the sense amplifier selectively in accordance with the invert/non-invert signals produced by the address logic.
In accordance with another embodiment of the invention, a memory is provided having an array of rows and columns of memory cells. A plurality of sense amplifiers, each one having a true terminal and a compliment terminal, is included. A plurality of pairs of bit lines is included, each one of the pairs of lines being coupled a corresponding one of the plurality of sense amplifiers. One of the bit lines in the pair is connected to a first portion of the memory cells in a first one of the columns of such cells and to a first portion of the memory cells in a second one of the columns of the memory cells. The other one of the bits lines in the pair is connected to a second portion of the memory cells in the first one of the columns of such memory cells and to a second portion of the memory cells in the second one of the columns of the memory cells. One of the lines in each pair of bit lines is coupled to the true terminal of the coupled one of the sense amplifiers and the other one of the lines of such pair of lines is coupled to the compliment terminal of the coupled one of the sense amplifiers. A plurality of word lines is included, each one being connected to a corresponding one of the rows of memory cells. An address logic section is fed by column address signals fed to the bit lines and row address signals coupled to the word lines for producing invert/non-invert signals in accordance with the fed row and column address signals. A plurality of inverters is included each one is coupled to a corresponding one of the sense amplifiers for inverting data fed to or read from the sense amplifier selectively in accordance with the invert/non-invert signals produced by the address logic.
In one embodiment, each one of the memory cells in one of the rows thereof is coupled is the true terminal of the plurality of sense amplifiers and each one the memory cells in another one of the rows thereof is coupled is the compliment terminal of the plurality of sense amplifiers.
In one embodiment, one portion of the memory cells in one of the rows thereof is coupled is the true terminal of one of the plurality of sense amplifiers and another portion of the memory cells in such one of the rows thereof is coupled is the compliment terminals of another one of the plurality of sense amplifiers.
In one embodiment, adjacent ones of the memory cells in such one of the rows are the connected to the true and compliment terminals of a corresponding pair of the sense amplifiers, respectively.
In one embodiment, the address logic section is enabled in response to a test signal and wherein when such test signal is applied to the address logic the memory cells in the array are programmed to bits of data having the same logic state.